US 2025/0167103 A1 · LOW RESISTANCE VIA STRUCTURE

Abstract

A homogeneous interconnect structure including a first region vertically aligned above a second region, the first region includes a first width at an upper horizontal surface and a second width at a lower horizontal surface, the first width is greater than the second width, the second region includes a third width, the third width is greater than the second width. A homogeneous interconnect structure including a first region vertically aligned above a second region, the first region includes a first width at an upper horizontal surface and a second width at a lower horizontal surface, the first width is greater than the second width, and the second region includes a third width at an upper horizontal surface and a fourth width at a lower horizontal surface, the third width is less than the fourth width.

Claims20

Dependent claims

A semiconductor structure comprising:

a homogeneous interconnect structure embedded in a dielectric layer, wherein the homogeneous interconnect structure comprises an upper region vertically aligned above a lower region;
the first region comprises a first width at an upper horizontal surface of the upper region and a second width at a lower horizontal surface of the upper region, wherein the first width is greater than the second width;
and
the lower region comprises a third width, wherein the third width is greater than the second width.

1 more element

Dependencies are inferred from the claim text.

Low resistance via structure

Life of this patent

Low resistance via structure

Life of this patent

Abstract

Claims20