Read offset compensator for adjusting reference resistance using coarse offset reference resistance and fine offset reference resistance, and memory device including the same

A memory device comprising:

• memory cell array comprising a plurality of memory cells;
• a row decoder connected to the memory cell array through word lines;
• a column decoder connected to the memory cell array through bit lines and source lines;
• a sense amplifier configured to read data stored in selected memory cells by detecting the difference between the source line voltage and the reference voltage during a read operation;
• and
• a controller configured to have a read offset compensator for performing an offset reference resistance compensation,
• wherein the read offset compensator is configured to:
• receive output data from the sense amplifier,
• search for a number of fail bits of the output data to determine a coarse offset reference resistance,
• detect a number of fail bits of first output data within a first reference resistance range based on the coarse offset reference resistance to determine a first fine offset reference resistance,
• search for a number of fail bits of second output data within a second reference resistance range based on the coarse offset reference resistance to determine a second fine offset reference resistance, and
• adjust a reference resistance for the read operation using the coarse offset reference resistance and fine offset reference resistances, the fine offset reference resistances comprising resistances from the first fine offset reference resistance to the second fine offset reference resistance.

An offset reference resistance compensation method for a memory device, the method being executed by at least one processor, and the method comprising:

• searching for a number of fail bits of output data output from a memory cell array of the memory device;
• determining a coarse offset reference resistance;
• searching for a number of fail bits of a first output data within a first reference resistance range based on the coarse offset reference resistance,
• determining a first fine offset reference resistance;
• searching for a number of fail bits of the second output data within a second reference resistance range based on the coarse offset reference resistance,
• determining a second fine offset reference resistance;
• and
• adjusting a reference resistance for a read operation using the coarse offset reference resistance and fine offset reference resistances, the fine offset reference resistances comprising resistances from the first fine offset reference resistance to the second fine offset reference resistance.