Shift register, gate driving circuit and display apparatus

A shift register, comprising:

• a voltage regulating circuit electrically connected to a light-emitting signal input terminal, a first clock signal terminal, a second clock signal terminal, a first node, and a second node, and configured to adjust voltages at the first node and the second node in response to control of signals provided by the light-emitting signal input terminal, the first clock signal terminal, and the second clock signal terminal;
• a light-emitting cascade output circuit electrically connected to a first power terminal, a second power terminal, a light-emitting cascade signal output terminal, the first node, and the second node, and configured to write a second operating voltage provided by the second power terminal to the light-emitting cascade signal output terminal in response to control of the voltage at the first node, and write a first operating voltage provided by the first power terminal to the light-emitting cascade signal output terminal in response to control of the voltage at the second node;
• a light-emitting driving output circuit electrically connected to a fifth power terminal, a third power terminal, a light-emitting control driving signal output terminal, the second node, the first node, and configured to write a third operating voltage provided by the third power terminal to the light-emitting control driving signal output terminal in response to control of the voltage at the first node, and to write a fifth operating voltage provided by the fifth power terminal to the light-emitting control driving signal output terminal in response to control of the voltage at the second node;
• and
• a first anti-leakage circuit electrically connected to the light-emitting cascade output circuit at a first anti-leakage node, and further electrically connected to the first node, the second node, the second power terminal, and a fourth power terminal, and configured to write a fourth operating voltage provided by the fourth power terminal to the first anti-leakage node in response to control of the voltage at the second node.