Pixel driving circuit and display panel

A display panel, comprising a pixel driving circuit, wherein the pixel driving circuit comprises:

• a driving transistor, wherein a gate of the driving transistor is coupled to a first node, a first electrode of the driving transistor is coupled to a second node, and a second electrode of the driving transistor is coupled to a third node;
• a data write circuit, coupled to the second node and a data signal terminal, and configured to transmit a signal of the data signal terminal to the second node in response to a signal of a first gate driving signal terminal;
• a threshold compensation circuit, coupled to the first node, the third node and a second gate driving signal terminal, and configured to communicate the first node with the third node in response to a signal of the second gate driving signal terminal;
• a first capacitor, coupled between the first node and the first gate driving signal terminal;
• a second capacitor, coupled between the first node and the second gate driving signal terminal;
• a first reset circuit, coupled to the first node, a first initial signal terminal and a first reset signal terminal, and configured to transmit a signal of the first initial signal terminal to the first node in response to a signal of the first reset signal terminal;
• and
• a second reset circuit, coupled to the second node and a first power terminal, and configured to transmit a signal of the first power terminal to the second node in response to a control signal,
• the first reset circuit comprises:
• a first transistor, wherein a gate of the first transistor is coupled to the first reset signal terminal, a first electrode of the first transistor is coupled to the first initial signal terminal, and a second electrode of the first transistor is coupled to the first node;
• the second reset circuit comprises:
• an eighth transistor, wherein a gate of the eighth transistor is configured to receive the control signal, a first electrode of the eighth transistor is coupled to the first power terminal, and a second electrode of the eighth transistor is coupled to the second node;
• wherein a width-to-length ratio of a channel of the eighth transistor is smaller than a width-to-length ratio of a channel of the first transistor channel.

A display panel, comprising a pixel driving circuit, wherein the pixel driving circuit comprising:

• a driving transistor;
• a N-type second transistor, wherein a gate of the N-type second transistor is coupled to a second gate line and a third gate line, a first electrode of the N-type second transistor is coupled to a gate of the driving transistor, and a second electrode of the N-type second transistor is coupled to a second electrode of the driving transistor;
• a P-type fourth transistor, wherein a gate of the P-type fourth transistor is coupled to a first gate line, a first electrode of the P-type fourth transistor is coupled to a data line, and a second electrode of the P-type fourth transistor is coupled to a first electrode of the driving transistor;
• a first capacitor, wherein a first electrode of the first capacitor is coupled to the first gate line, and a second electrode of the first capacitor is coupled to the gate of the driving transistor;
• and
• a second capacitor, wherein a first electrode of the second capacitor is coupled to the third gate line, and a second electrode of the second capacitor is coupled to the gate of the driving transistor;
• a first reset circuit, coupled to the gate of the driving transistor, a first initial signal terminal and a first reset signal terminal, and configured to transmit a signal of the first initial signal terminal to the gate of the driving transistor in response to a signal of the first reset signal terminal;
• and
• a second reset circuit, coupled to the first electrode of the driving transistor and a first power terminal, and configured to transmit a signal of the first power terminal to the first electrode of the driving transistor in response to a control signal,
• the first reset circuit comprises:
• a first transistor, wherein a gate of the first transistor is coupled to the first reset signal terminal, a first electrode of the first transistor is coupled to the first initial signal terminal, and a second electrode of the first transistor is coupled to the gate of the driving transistor;
• the second reset circuit comprises:
• an eighth transistor, wherein a gate of the eighth transistor is configured to receive the control signal, a first electrode of the eighth transistor is coupled to the first power terminal, and a second electrode of the eighth transistor is coupled to the first electrode of the driving transistor;
• wherein a width-to-length ratio of a channel of the eighth transistor is smaller than a width-to-length ratio of a channel of the first transistor channel.