Image signal processor

An image signal processor comprising:

• a first throttle buffer configured to receive first to third image signals from an image sensor, buffer the first to third image signals, and output the buffered first to third image signals, the first image signal including an N-th line and an (N+1)-th line subsequent to the N-th line;
• a first module configured to receive the first to third image signals, perform a first calculation on each of the first to third image signals, and output first to third calculated image signals respectively corresponding to the first to third image signals;
• a first splitter configured to receive the first to third calculated image signals, split the first to third calculated image signals, and send the first calculated image signal to a first path;
• a throughput checking circuit configured to
• receive a period signal of the first image signal from the first throttle buffer including information about a first time-point at which the N-th line of the first image signal is input to the first throttle buffer and a second time-point at which the (N+1)-th line of the first image signal is input into the first throttle buffer, and a valid signal of the first image signal from the first throttle buffer including information about a third time-point at which the N-th line of the first image signal is output from the first throttle buffer, and
• output a first stall counting enable signal at a logic high, in response to the second time-point being earlier than the third time-point;
• and
• a first stall counting circuit configured to count a first stall signal input from the first path, in response to receiving the first stall counting enable signal at a logic high.

An image signal processor comprising:

• a throttle buffer configured to receive a first image signal from an image sensor, buffer the first image signal, and output the buffered first image signal;
• a first module configured to receive the first image signal, perform a first calculation on the first image signal to generate a second image signal, and output the second image signal;
• a first splitter configured to receive the second image signal, split the second image signal, and send a third image signal corresponding to part of the second image signal to a first path, the third image signal including an N-th line and an (N+1)-th line subsequent to the N-th line;
• a buffer checking circuit configured to
• receive a memory status signal from the throttle buffer including information about a capacity of one line included in the third image signal, a total capacity of the throttle buffer, and a usage capacity of the throttle buffer, and
• output a first stall counting enable signal at a logic high, in response to a ratio of the usage capacity of the throttle buffer to the total capacity of the throttle buffer being greater than a ratio of the capacity of one line included in the third image signal to the total capacity of the throttle buffer;
• a throughput checking circuit configured to
• receive a period signal of the third image signal from the throttle buffer including information about a first time-point at which the N-th line of the third image signal is input to the throttle buffer and a second time-point at which the (N+1)-th line of the third image signal is input to the throttle buffer, and a valid signal of the third image signal from the throttle buffer including information about a third time-point at which the N-th line of the third image is output from the throttle buffer, and
• output a second stall counting enable signal at a logic high, in response to the second time-point of the third image signal being earlier than the third-time point of the third image signal;
• and
• a stall counting circuit configured to count a stall signal input from the first path, in response to receiving one of the first stall counting enable signal at a logic high and the second stall counting enable signal at a logic high.