Error limiting protocol for the construction of two-qubit gates in an ion-trap quantum computing system

A quantum computing system, comprising:

• a quantum processor comprising a plurality of trapped ions, wherein each of the trapped ions having two frequency-separated states defining a qubit;
• a classical computer configured to:
• compute a control pulse to be applied to a pair of trapped ions in the quantum processor, wherein computing the control pulse comprises:
• computing a pulse function of the control pulse based on a phase-space closure condition and an auxiliary condition;
• and
• computing the pulse function of the control pulse further based on a gate angle condition;
• and
• a system controller configured to:
• apply the control pulse, having the computed pulse function, to the pair of trapped ions.

A quantum computing system comprising non-volatile memory having a number of instructions stored therein which, when executed by one or more processors, causes the quantum computing system to perform operations comprising:

• computing, by a classical computer, a control pulse to be applied to a pair of trapped ions in a plurality of trapped ions in a quantum processor, each of the plurality of trapped ions having two frequency-separated states defining a qubit, wherein computing the control pulse comprises:
• computing a pulse function of the control pulse based on a phase-space closure condition and an auxiliary condition;
• and
• computing the pulse function of the control pulse further based on the gate angle condition;
• and
• applying, by a system controller, the control pulse, having the computed pulse function, to the pair of trapped ions.