US 2025/0165765 A1 · COMBINATORIAL OPTIMIZATION ACCELERATED BY PARALLEL, SPARSELY COMMUNICATING, COMPUTE-MEMORY INTEGRATED HARDWARE

Abstract

A neuromorphic network may solve combinatorial optimization problems. The neuromorphic network may include variable neurons, a solution monitoring neuron, and one or more readout neurons. The variable neurons may each represent one binary variable in a combinatorial optimization problem. An internal state of a variable neuron may change as the variable flips. The internal state may be stored in a memory of the variable neuron. The variable neuron may spike when its internal state changes. One or more other variable neurons receiving the spike may determine whether to change their internal states based on the spike. The variable neurons may send their internal states to the solution monitoring neuron to compute a cost of the QUBO problem and determine whether a solution is found. A readout neuron may receive variable assignments resulting in the solution from at least some variable neurons and integrate the variable assignments into one message.

Claims20

Dependent claims

An apparatus, comprising:

a first neuron of a neural network, the first neuron comprising a first memory for storing a first variable, different values of the first variable corresponding to different states of the first neuron;
a second neuron of the neural network, the second neuron communicatively coupled to the first neuron and comprising a second memory for storing a second variable, different values of the second variable corresponding to different states of the second neuron, the second neuron to determine whether to modify its state based on a message from the first neuron;
and
a third neuron of the neural network, the third neuron communicatively coupled to the first neuron and the second neuron for computing a cost, using a cost function, from data received from the first neuron and data received from the second neuron and comprising a third memory for storing the cost.

1 more element

Dependencies are inferred from the claim text.

Combinatorial optimization accelerated by parallel, sparsely communicating, compute-memory integrated hardware

Life of this patent

Combinatorial optimization accelerated by parallel, sparsely communicating, compute-memory integrated hardware

Life of this patent

Abstract

Claims20