Neural network circuit, edge device and neural network operation process

A neural network circuit, comprising:

• a first memory unit that stores input data;
• a convolution operation circuit that performs a convolution operation on a weight and the input data stored in the first memory unit;
• a second memory unit that stores convolution operation output data from the convolution operation circuit;
• and
• a quantization operation circuit that performs a quantization operation on the convolution operation output data stored in the second memory unit;
• wherein
• the first memory unit stores a quantization operation output data from the quantization operation circuit;
• the convolution operation circuit performs the convolution operation on the quantization operation output data stored in the first memory unit as the input data;
• the convolution operation circuit performs the convolution operation on the input data stored in the first memory, and stores the convolution operation output data in the second memory;
• the quantization operation circuit performs a quantization operation on the convolution operation output data stored in the second memory, and stores the quantization operation output data in the first memory;
• and
• the convolution operation circuit performs a convolution operation on the quantization operation output data stored in the first memory as the input data, and stores the convolution operation output data in the second memory.