Modular interconnect for an integrated circuit device

A system comprising:

• a memory device comprising instructions stored thereon;
• a processing device coupled to the memory device and configured to execute the instructions, the instructions when executed cause the processing device to:
• receive a circuit design;
• generate connections within a network-on-chip (NoC) by analyzing the circuit design to detect a first connection attribute, wherein the first connection attribute defines a first NoC master unit (NMU) and a first NoC slave unit (NSU);
• and
• generate a first NoC configuration including the connections determined based on the first NMU and the first NSU.

A non-transitory computer readable medium comprising stored instructions, which when executed by a processing device, cause the processing device to:

• receive a circuit design;
• generate connections within a network-on-chip (NoC) by analyzing the circuit design to detect a first connection attribute, wherein the first connection attribute defines a first NoC master unit (NMU) and a first NoC slave unit (NSU);
• and
• generate a first NoC configuration including the connections determined based on the first NMU and the first NSU.