US 2025/0165690 A1 · UNDER TEST (DUT) PROCESSING FOR LOGIC OPTIMIZATION

Abstract

An example is a non-transitory computer-readable storage medium including stored instructions. The instruction, which when executed by one or more processors, cause the one or more processors to: obtain a representation of a design under test (DUT) and split the representation of the DUT into multiple partitions. The representation of the DUT includes optimizable leaf instances and timing paths between respective timing startpoints and timing endpoints. Splitting the representation of the DUT into multiple partitions is based on respective slacks of the timing endpoints. Each partition of the multiple partitions includes one or more timing endpoints of the timing endpoints and a transitive fan-in including one or more optimizable leaf instances along one or more timing paths of the timing paths that terminate at the respective one or more timing endpoints.

Claims20

Dependent claims

A non-transitory computer-readable storage medium comprising stored instructions, which when executed by one or more processors, cause the one or more processors to:

obtain a representation of a design under test (DUT), the representation of the DUT including optimizable leaf instances and timing paths between respective timing startpoints and timing endpoints;
and
split the representation of the DUT into multiple partitions based on respective slacks of the timing endpoints, each partition of the multiple partitions including one or more timing endpoints of the timing endpoints and a transitive fan-in including one or more optimizable leaf instances along one or more timing paths of the timing paths that terminate at the respective one or more timing endpoints.

Dependencies are inferred from the claim text.

Under test (dut) processing for logic optimization

Life of this patent

Under test (dut) processing for logic optimization

Life of this patent

Abstract

Claims20