US 2025/0165658 A1 · ITERATIVE GUIDED ARCHITECTURE DESIGN BASED ON SELF-OPTIMIZING ANALYTICAL MODELS

Abstract

Provided are systems, methods, and apparatuses for iterative guided architecture design based on self-optimizing analytical models. In one or more examples, the systems, devices, and methods include determining a figure of merit (FOM) of a reference architecture based on executing a workload on the reference architecture and measuring a hardware event associated with executing the workload. In some examples, the systems, devices, and methods include determining an analytical model based on the FOM and based on performing roofline analysis on the reference architecture. In some examples, the systems, devices, and methods include estimating performance of the workload on the target architecture based on the analytical model identifying an optimal design based on validating the analytical model on a plurality of architectures executing the workload.

Claims20

Dependent claims

A method of optimizing an architecture design, the method comprising:

determining a figure of merit (FOM) of a reference architecture based on executing a workload on the reference architecture and measuring a hardware event associated with executing the workload, the hardware event comprising a performance metric associated with at least one of a processor of the reference architecture, a memory of the reference architecture, or a storage device of the reference architecture;
determining an analytical model based on the FOM and based on performing roofline analysis on the reference architecture;
estimating performance of the workload on a target architecture based on the analytical model;
and
identifying an optimal design of the target architecture based on validating the analytical model on a plurality of architectures executing the workload.

2 more elements

A device, comprising:

at least one memory;
and
at least one processor coupled with the at least one memory configured to:
determine a figure of merit (FOM) of a reference architecture based on executing a workload on the reference architecture and measuring a hardware event associated with executing the workload, the hardware event comprising a performance metric associated with at least one of a processor of the reference architecture, a memory of the reference architecture, or a storage device of the reference architecture;
determine an analytical model based on the FOM and based on performing roofline analysis on the reference architecture;
estimate performance of the workload on a target architecture based on the analytical model;
and
identify an optimal design of the target architecture based on validating the analytical model on a plurality of architectures executing the workload.

5 more elements

A non-transitory computer-readable medium storing code that comprises instructions executable by a processor of a device to:

determine a figure of merit (FOM) of a reference architecture based on executing a workload on the reference architecture and measuring a hardware event associated with executing the workload, the hardware event comprising a performance metric associated with at least one of a processor of the reference architecture, a memory of the reference architecture, or a storage device of the reference architecture;
determine an analytical model based on the FOM and based on performing roofline analysis on the reference architecture;
estimate performance of the workload on a target architecture based on the analytical model;
and
identify an optimal design of the target architecture based on validating the analytical model on a plurality of architectures executing the workload.

2 more elements

Dependencies are inferred from the claim text.

Iterative guided architecture design based on self-optimizing analytical models

Life of this patent

Iterative guided architecture design based on self-optimizing analytical models

Life of this patent

Abstract

Claims20