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US 2025/0165429 A1Published application
Multi-level hierarchical routing matrices for pattern-recognition processors
AssigneeMicron Technology, Inc.
InventorsHarold B Noyes, David R. Brown
Life of this patent
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Abstract
Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.
Claims20
An apparatus, comprising:
- a pattern match engine, comprising:
- first detection logic configured to detect a first match of a first portion of a pattern to be matched;
- and
- second detection logic configured to detect a second match of a second portion of the pattern to be matched.
1 more element
A method, comprising:
- detecting, via first detection logic of a pattern match engine, a first match of a first portion of a pattern to be matched;
- and
- detecting, via second detection logic of the pattern match engine, a second match of a second portion of the pattern to be matched.
A device, comprising:
- first detection logic configured to detect a first match of a first portion of a pattern to be matched;
- and
- an input selection circuit configured to provide an input to the first detection logic upon which detection of the first match is determined.
Dependencies are inferred from the claim text.