Techniques and devices for configurable memory encryption and authentication

A method comprising:

• storing, at a first memory location, a plurality of ciphertext blocks;
• storing, at the first memory location, an authentication tag for the plurality of ciphertext blocks;
• storing, at a second memory location, an error correction code (ECC) for the plurality of ciphertext blocks;
• retrieving, from the first memory location, the plurality of ciphertext blocks;
• retrieving, from the first memory location, the authentication tag;
• obtaining, using the plurality ciphertext blocks, a control authentication tag for the plurality of ciphertext blocks;
• and
• determining, responsive to a comparison of the authentication tag to the control authentication tag, whether to retrieve the ECC.

A cryptographic processor comprising:

• one or more cipher circuits configured to:
• process a plurality of plaintext blocks and to output a plurality of ciphertext blocks, wherein each of the plurality of ciphertext blocks comprises an encrypted respective block of the plurality of plaintext blocks;
• and
• one or more processing circuits configured to:
• in a first selectable mode, process sequentially the plurality of ciphertext blocks to obtain an authentication value;
• in a second selectable mode, perform no processing;
• wherein the one or more cipher circuits are further configured to:
• in the first selectable mode, encrypt the authentication value to obtain an encrypted authentication value;
• and
• in the second selectable mode, perform no processing.