System Control Using Sparse Data

A method, comprising:

• receiving, by a memory, information indicative of a request to perform a read operation, wherein the information includes an address;
• comparing the address to at least one entry of a plurality of entries included in a sparse array circuit, wherein a given entry of the plurality of entries corresponds to an address location in the memory, in which a sparse data pattern is stored;
• and
• in response to determining that the address matches a particular entry of the plurality of entries:
• disabling, by a control circuit, a timing signal to ones of a plurality of sample circuits associated with the address;
• and
• responding, by the control circuit, to the read operation with the sparse data pattern.

An apparatus, comprising:

• a memory circuit including a plurality of rows of memory cells;
• a data capture circuit, including a plurality of sample circuits, configured to sample respective bit values from a plurality of data cells from a selected row of the plurality of rows of the memory circuit;
• and
• a control circuit configured to:
• compare a received read address associated with a particular row of the plurality of rows to a plurality of addresses associated with locations in the memory circuit where data that matches a sparse data pattern is stored;
• in response to a determination that the received read address is excluded from the plurality of addresses, use the data capture circuit to sample bit values associated with the received read address;
• and
• in response to a determination that the received read address is included within the plurality of addresses, disable power to ones of the plurality of sample circuits associated with the received read address.