Self-contained and configurable debugging mechanism for stream-based hardware accelerators

A system, comprising:

• a host device;
• and
• a hardware accelerator, the hardware accelerator including:
• a plurality of functional circuits;
• a stream switch;
• a plurality of direct memory access (DMA) channels coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits;
• and
• a debug and trace unit coupled to the stream switch, wherein in operation, the debug and trace unit monitors a set of data signals to and from the stream switch via wired probes and implements one or more event counters, one or more triggers, and one or more tracers using components internal to the hardware accelerator including one or more registers of the hardware accelerator, and wherein the one or more tracers output trace data packets via the stream switch.

A method, comprising:

• streaming data between a plurality of direct memory access (DMA) channels of a hardware accelerator and a plurality of functional circuits of the hardware accelerator via a stream switch;
• implementing debug and trace functions within the hardware accelerator based on configurations obtained via configuration registers;
• monitoring data signals to and from the stream switch;
• and
• outputting trace data via the stream switch.

A non-transitory computer-readable medium having contents which cause a system including one or more processors to perform actions comprising:

• streaming data between a plurality of direct memory access (DMA) channels of a hardware accelerator and a plurality of functional circuits of the hardware accelerator via a stream switch;
• implementing debug and trace functions within the hardware accelerator based on configurations obtained via configuration registers;
• monitoring data signals to and from the stream switch;
• and
• outputting trace data via the stream switch.