Memory controller managing read level information, memory system including the same, and operating method of the memory controller

A memory controller for communicating with a memory device comprising a plurality of memory chips, the memory controller comprising:

• a processor configured to control a read operation on the memory device;
• a read level (RL) information management circuit configured to, with respect to a first super block comprising first blocks of the plurality of memory chips, set a read level calculated with respect to at least one first block as first super block RL information corresponding to the first super block, and set a read level calculated with respect to the first blocks of the plurality of memory chips as chip RL information corresponding to the corresponding memory chip;
• a first memory configured to store a plurality of pieces of super block RL information respectively corresponding to a plurality of super blocks provided in the plurality of memory chips;
• and
• a second memory configured to store a plurality of chip RL information respectively corresponding to the plurality of memory chips,
• wherein, during a read operation on the memory device, the processor is further configured to control the read operation according to super block RL information read from the first memory, and, based on a failure occurring in data read based on the super block RL information, control the read operation according to chip RL information read from the second memory.

A memory system comprising:

• a memory device comprising a plurality of memory chips, each of the plurality of memory chips comprising a plurality of blocks, wherein first blocks of the plurality of memory chips constitute a first super block;
• and
• a memory controller configured to control a read operation on the memory device according to a request from a host,
• wherein the memory device is configured to:
• read data of a first block of a first memory chip according to first super block read level (RL) information that is commonly set for the first blocks of the first super block and indicates a first read level;
• and
• based on a failure occurring in the data read based on the first super block RL information, read the data of the first block of the first memory chip according to first chip RL information that is set separately with respect to the first memory chip and indicates a second read level different from the first read level.