Separate branch target buffers for different levels of calls

A method implemented in a computing device, the method comprising:

• executing in a program in a processor, wherein the processor has a plurality of branch target buffers, and the program has a plurality of routines;
• and
• allocating the plurality of branch target buffers to execution of the plurality of routines respectively;
• storing branch prediction information of each respective routine in a respective branch target buffer;
• and
• executing the respective routine by accessing branch prediction information only in the respective branch target buffer allocated to the respective routine.

A processor, comprising:

• at least one execution unit;
• and
• an instruction fetch stage having a first branch target buffer and a second branch target buffer;
• wherein during execution of a program having a first routine and a second routine:
• the first branch target buffer stores branch prediction information of the first routine;
• the second branch target buffer stores branch prediction information of the second routine;
• execution of the first routine only accesses the first branch target buffer;
• and
• execution of the second routine only accesses the second branch target buffer.