Method and system for rounding a subnormal number

A hardware implementation for rounding a floating-point number in an Extended Exponent Range (EER), that would be a denormal floating-point number represented in an Unextended Exponent Range (UER), the hardware implementation comprising:

• an arithmetic unit configured to:
• receive a plurality of input numbers in the EER representation, each input number comprising a sign bit (si), exponent bits (ei) and mantissa bits (mi), and
• perform an arithmetic operation to produce an output number in the EER representation comprising a sign bit (sa), an exponent bits (ea) and mantissa bits (ma);
• a mask constructing unit configured to construct a rounding mask based on the exponent bits (ea) computed by the arithmetic operation;
• and
• a rounding unit configured to apply the rounding mask to the output number in the EER representation to round the output number to correct position as if rounding in the UER representation.