Memory controller and memory system including the same

Abstract

A memory controller includes a response buffer configured to store responses provided from a memory device; a congestion monitoring circuit configured to monitor a congestion degree at an egress port of the memory controller; a priority control circuit configured to adjust a priority of commands to process second commands corresponding to an internal operation prior to first commands corresponding to a host-requested operation, based on the congestion degree at the egress port and a fill-level of the response buffer; and a command generation circuit configured to schedule the first commands and the second commands according to the priority and output the scheduled commands to the memory device.

Dependencies are inferred from the claim text.