System and method for memory bad block management

A method of operating a memory system, wherein the memory system includes a memory module including a plurality of semiconductor memory devices and a memory controller connected to at least one host through a serial interface, and is configured to control the plurality of semiconductor memory devices, and wherein each of the plurality of semiconductor memory devices includes a memory cell array including a normal cell region and a redundancy region, the method comprising:

• performing, in each of the plurality of semiconductor memory devices, a test on a plurality of memory cells in the memory cell array, in a test mode;
• storing addresses of defective memory cell rows that are unrepairable with a redundancy resource of the redundancy region as unrepairable addresses in a nonvolatile storage in the memory controller, based on a result of the test;
• allocating, by the memory controller, a portion of the normal cell regions of at least one of the plurality of semiconductor memory devices as a reserved region based on the unrepairable addresses;
• and
• remapping, by the memory controller, the unrepairable addresses to consecutive physical addresses of the reserved region, in response to the at least one host accessing defective memory cell rows corresponding to the unrepairable addresses.

A memory system comprising:

• a memory module including a plurality of semiconductor memory devices;
• and
• a memory controller connected to at least one host through a serial interface, the memory controller configured to control the plurality of semiconductor memory devices,
• wherein each of the plurality of semiconductor memory devices includes a memory cell array that includes a normal cell region and a redundancy region, and
• wherein each of the plurality of semiconductor memory devices is configured to provide the memory controller with an address of at least a first defective memory cell row from among defective memory cell rows in the normal cell region as an unrepairable address information, the at least first defective memory cell row being unrepairable with a redundancy resource of the redundancy region,
• wherein the memory controller comprises:
• a bad block manager configured to allocate a portion of the normal cell regions of at least one of the plurality of semiconductor memory devices as a reserved region based on the unrepairable address information;
• and
• a remapping engine configured to remap a first unrepairable address to a first physical address of the reserved region in response to a first host physical address from the at least one host matching the first unrepairable address in the unrepairable address information, and to remap a second unrepairable address to a second physical address of the reserved region in response to a second host physical address from the at least one host matching the second unrepairable address in the unrepairable address information,
• wherein the first physical address and the second physical address are consecutive.