System on chip for reducing wake-up time, method of operating same, and computer system including same

A system on chip (SoC) comprising:

• a first memory comprising a first boot loader for performing a booting sequence;
• and
• a second memory comprising a second boot loader,
• wherein the SoC is configured to:
• supply power to both of the first memory and the second memory based on the SoC operating under a first mode,
• cut off the power to the first memory and supply the power to the second memory based on the SoC operating under a second mode, and
• perform a wake-up sequence based on the SoC operating under a third mode.

A system on chip (SoC) comprising:

• a first memory comprising a first boot loader for performing a booting sequence;
• a second memory comprising a second boot loader;
• and
• a memory controller configured to load an operating system to an external memory based on one of the first boot loader or the second boot loader,
• wherein, the memory controller is configured to:
• supply power to both of the first memory and the second memory based on the SoC operating under a first mode,
• cut off the power to the first memory and supply the power to the second memory based on the SoC operating under a second mode,
• perform a wake-up sequence based on the SoC entering a third mode from the second mode, and
• jump to an address of the operating system based on the second boot loader of the second boot loader based on the SoC operating under the third mode.