Deskew and clock domain crossing for multilane link

A multilane clock crossing apparatus comprising:

• a plurality of FIFO deskew buffers, wherein each deskew buffer receives and buffers a corresponding one of the plurality of data streams from a corresponding lane of the multilane link;
• wherein for each deskew buffer,
• the corresponding data stream is clocked into the deskew buffer using a corresponding recovered clock signal recovered from the data stream corresponding to the deskew buffer, wherein the recovered clock signal is independent of a destination clock domain, and
• the data stream is clocked out of the deskew buffer using a destination clock signal of the destination clock domain.

A method comprising:

• receiving, at a destination device having a destination clock domain, a plurality of data streams from a source device having a source clock domain which is independent of the destination clock domain, each of the plurality of data streams being received via a corresponding lane of a multilane data link;
• and
• for each of the plurality of received data streams,
• recovering a corresponding recovered clock signal from the received data stream, and
• clocking data of the received data stream into a corresponding deskew buffer using the recovered clock signal from the received data stream;
• and
• clocking data of the received data stream out of corresponding deskew buffer using a destination clock signal of the destination clock domain, thereby generating a corresponding generated data stream that is synchronized with the destination clock signal.