Command signal clock toggling by a controller

An apparatus, comprising:

• a memory device interface comprising:
• a first flip-flop circuit to receive command data from a command data processing circuit of a memory device;
• a second flip-flop circuit to receive clock signals from a clock processing circuit of the memory device;
• a first first-in first-out (FIFO) device to receive output command data from the first flip-flop circuit;
• and
• a second FIFO device to receive output clock data from the second flip-flop circuit;
• and
• a controller configured to:
• generate a plurality of command signals to be provided to a memory device to generate command data in response to the plurality of command signals;
• generate a first plurality of clock signals that correspond to the plurality of command signals to be provided to the memory device;
• and
• generate a second plurality of clock signals that exceed a quantity of the plurality of command signals to be provided to the memory device, wherein the memory device is to generate clock signals in response to the first plurality of clock signals and the second plurality of clock signals to be provided to the second flip-flop circuit.

A system comprising:

• a memory sub-system comprising a non-volatile memory device;
• and
• a processing device coupled to the memory sub-system, wherein the processing device is configured to:
• generate a first plurality of clock signals that correspond to a first plurality of command signals and a second plurality of clock signals;
• provide the first plurality of clock signals, the second plurality of clock signals, and the plurality of command signals to the non-volatile memory device;
• receive, at a first-in first-out (FIFO) device, a second plurality of command signals that correspond to the first plurality of command signals and a third plurality of clock signals that correspond to the first plurality of clock signals
• receive, at the FIFO device, a third plurality of command signals and a fourth plurality of clock signals that correspond to the second plurality of clock signals;
• identify a first set of output values based on the received second plurality of command signals and the third plurality of clock signals within the FIFO device;
• and
• ignore a second set of output values based on the third plurality of command signals and the fourth plurality of clock signals.