Method of using circuit test structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChing-Fang CHEN, Hsiang-Tai LU, Chih-Hsien LIN
Life of this patent
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Abstract
A method of testing a circuit structure includes applying a voltage to a first testing site, wherein the testing site is electrically connected to a conductive line which traces a perimeter of a chip, and the chip is between an interposer and the conductive line. The method further includes measuring a current at a second testing site to determine an integrity of the conductive line, wherein the interposer is between the first testing site and the second testing site.
Claims20
A method of testing a circuit structure, the method comprising:
- applying a voltage to a first testing site, wherein the testing site is electrically connected to a conductive line which traces a perimeter of a chip, and the chip is between an interposer and the conductive line;
- and
- measuring a current at a second testing site to determine an integrity of the conductive line, wherein the interposer is between the first testing site and the second testing site.
A method of testing a circuit structure, the method comprising:
- applying a voltage to a first testing site on a first side of an interposer, wherein the first testing site is electrically connected to a conductive line tracing a perimeter of a chip, and the interposer is between the first testing site and the chip;
- and
- measuring a current at a second testing site on the first side of the interposer to determine an integrity of the circuit structure, wherein the first testing site is electrically connected to the second testing site through the conductive line.
A method of testing a circuit structure, the method comprising:
- applying a voltage to a first testing site on an interposer using a first test circuit on the interposer, wherein the first testing site is electrically connected to a conductive line on a chip, and the interposer is between the first testing site and the chip;
- and
- measuring a resistance along the conductive line using a second test circuit on the chip to determine an integrity of the circuit structure.
Dependencies are inferred from the claim text.