Display device and electronic device including the same

A display device comprising:

• a light-emitting element;
• a driving transistor configured to supply a driving current to the light-emitting element;
• a compensate transistor including a first sub-transistor and a second sub-transistor, the first sub-transistor including an output terminal electrically connected to a gate electrode of the driving transistor, the second sub-transistor including an output terminal electrically connected to an input terminal of the first sub-transistor and an input terminal electrically connected to an output terminal of the driving transistor;
• an initialization transistor including a third sub-transistor and a fourth sub-transistor, the third sub-transistor including an output terminal electrically connected to the gate electrode of the driving transistor, the fourth sub-transistor including an output terminal electrically connected to an input terminal of the third sub-transistor and an input terminal electrically connected to an initialization voltage line;
• a first blocking pattern disposed on the gate electrode of the driving transistor and disposed between a portion of an active pattern intersecting with the output terminal of the first sub-transistor and the output terminal of the third sub-transistor and the third sub-transistor;
• a second blocking pattern disposed on the first blocking pattern and overlapping at least a portion of the first sub-transistor;
• and
• a third blocking pattern disposed on the first blocking pattern and overlapping the third sub-transistor and at least a portion of the fourth sub-transistor.

An electronic device comprising:

• a display device;
• and
• a power supply configured to provide power to the display device,
• wherein the display device comprises:
• a substrate;
• an active pattern disposed on the substrate and including a first area, a first channel area disposed adjacent to the first area in a first direction, a second area spaced apart from the first area in a second direction intersecting the first direction, and a second channel area disposed between the first area and the second area;
• a first conductive layer disposed on the active pattern and including a first gate voltage line overlapping the first channel area and a second gate voltage line overlapping the second channel area;
• a second conductive layer disposed on the first conductive layer and including a bias line overlapping the second area and a first stabilization electrode overlapping a portion of the first area;
• a first electrode pattern disposed on the second conductive layer and including a first blocking pattern protruding from a portion overlapping the first area toward the second channel area;
• a second electrode pattern disposed on the first electrode pattern and including a second blocking pattern protruding from a portion overlapping the first electrode pattern toward the first channel area and overlapping the first channel area;
• and
• a first initialization voltage line disposed on the first electrode pattern, including a third blocking pattern overlapping the second channel area, and extending along the first direction.