Active Wafer-Scale Reconfigurable Logic Fabric for AI and High-Performance Embedded Computing

Abstract

A novel active and passive wafer-scale fabric is disclosed that allows for the integration of very-large-scale integrated circuits (ICs) with hundreds of closely-spaced bare-die chips such as memory, GPUs, FPGAs and AI accelerators into a single wafer. The wafer-scale logic fabric allows the tiling of known good chips to make systems that perform as a single-chip monolithic device, despite comprising several smaller heterogeneous chips. This approach enables higher bandwidth and lower connectivity loss than conventional circuit board packaging, which is especially critical for AI computing and signal/image processing applications. Further, it also allows for multiple levels of high-density connections, since this architecture allows wiring between chips to be as small as the wiring within a chip. This wafer-scale platform combined with heterogeneous IP block/chiplets and μ-bump integration produces a chip-like wiring for the wafer-scale heterogeneous multi-chip system where part of chip can be removed or reconfigured.

Dependencies are inferred from the claim text.