Stacked transistor device formed using multi-layer dummy gate

A stacked field-effect transistor (FET) device comprising:

• a lower FET comprising lower channel layers and a lower gate material that is between the lower channel layers;
• an upper FET that is on the lower FET, the upper FET comprising upper channel layers and an upper gate material that is between the upper channel layers;
• an isolation region that separates the lower channel layers from the upper channel layers;
• and
• an insulating layer that separates the lower gate material from the upper gate material and is adjacent a sidewall of the isolation region.

A method of forming a stacked field-effect transistor (FET) device, the method comprising:

• forming a nanosheet stack and a multi-layer dummy gate structure on the nanosheet stack, wherein the nanosheet stack comprises lower channel layers and upper channel layers that are on the lower channel layers, and wherein the multi-layer dummy gate structure comprises an upper semiconductor sacrificial layer, a lower semiconductor sacrificial layer, and an etch-stop layer that is between the lower semiconductor sacrificial layer and the upper semiconductor sacrificial layer;
• removing the upper semiconductor sacrificial layer to expose an upper surface of the etch-stop layer;
• forming an upper gate material between the upper channel layers and on the upper surface of the etch-stop layer;
• removing the lower semiconductor sacrificial layer to expose a lower surface of the etch-stop layer, after forming the upper gate material;
• and
• forming a lower gate material between the lower channel layers, after removing the lower semiconductor sacrificial layer.