Semiconductor device having work-function metal and method of forming the same

A method of forming a semiconductor device, comprising:

• forming a first fin active area and a second fin active area on a substrate;
• forming an insulating layer on the substrate, the insulating layer covering the first and second fin active areas;
• forming a first gate electrode covering a side surface of the first fin active area and crossing the first fin active area, the first gate electrode including,
• a first layer in the first fin active area and including Ti and N,
• a second layer on the first layer and including Ti and N,
• a third layer on the second layer and including Ti, Al and C,
• a fourth layer on the third layer and including Ti and N, and
• a fifth layer on the fourth layer and including W;
• forming a second gate electrode covering a side surface of the second fin active area and crossing the second fin active area, the second gate electrode including,
• a sixth layer in the second fin active area and including Ti and N,
• a seventh layer on the sixth layer and including Ti, Al and C, and
• a eighth layer on the seventh layer and including Ti and N;
• and
• wherein a thickness of the first layer ranges from 1 nm to 2 nm,
• wherein a thickness of the third layer ranges from 3 nm to 5 nm,
• wherein a thickness of the sixth layer ranges from 1 nm to 2 nm
• wherein a thickness of the seventh layer ranges from 3 nm to 5 nm, and
• wherein a width of the first gate electrode is greater than a width of the second gate electrode.

A method of forming a semiconductor device, comprising:

• forming a first fin active area and a second fin active area on a substrate;
• forming a first gate electrode covering a side surface of the first fin active area and crossing the first fin active area, the first gate electrode including,
• a first layer in the first fin active area and including Ti and N,
• a second layer on the first layer and including Ti and N,
• a third layer on the second layer and including Ti, Al and C,
• a fourth layer on the third layer and including Ti and N, and
• a fifth layer on the fourth layer and including W;
• forming a second gate electrode covering a side surface of the second fin active area and crossing the second fin active area, the second gate electrode including,
• a sixth layer in the second fin active area and including Ti and N,
• a seventh layer on the sixth layer and including Ti, Al and C, and
• a eighth layer on the seventh layer and including Ti and N;
• and
• wherein a thickness of the first layer ranges from 1 nm to 2 nm,
• wherein a thickness of the third layer ranges from 3 nm to 5 nm,
• wherein a thickness of the sixth layer ranges from 1 nm to 2 nm
• wherein a thickness of the seventh layer ranges from 3 nm to 5 nm,
• wherein the second gate electrode does not include W, and
• wherein a width of the first gate electrode is different from a width of the second gate electrode.