Dual side cut staggered stacked field effect transistor

A semiconductor device comprising:

• a plurality of nanodevices including a plurality of upper transistors and a plurality of lower transistors, wherein the plurality of nanodevices include an upper active region and a lower active region that are offset from each other across the plurality of upper transistors and the plurality of lower transistors;
• a first frontside gate cut dielectric pillar and a second frontside gate cut dielectric pillar located adjacent to and parallel to a first nanodevice and a second nanodevice, respectively, of the plurality of nanodevices along an x-axis, wherein a backside surface of the first frontside gate cut dielectric pillar and a backside surface of the second frontside gate cut dielectric pillar each extend a first width along a y-axis;
• and
• a first backside dielectric fill and a second backside dielectric fill in direct contact with the backside surface of the first frontside gate cut dielectric pillar and the backside surface of the second frontside gate cut dielectric pillar, respectively, wherein a frontside surface of the first backside dielectric fill and a frontside surface of the second backside dielectric fill each extend a second width along the y-axis, and wherein the second width is greater than the first width.

A semiconductor device comprising:

• a plurality of nanodevices including a plurality of upper transistors and a plurality of lower transistors, wherein the plurality of nanodevices include an upper active region and a lower active region that are offset from each other across the plurality of upper transistors and the plurality of lower transistors, wherein the upper active region includes an upper source/drain, and wherein the lower active region includes a lower source/drain;
• a first frontside gate cut dielectric pillar and a second frontside gate cut dielectric pillar located adjacent to and parallel to a first nanodevice and a second nanodevice, respectively, of the plurality of nanodevices along an x-axis, wherein a backside surface of the first frontside gate cut dielectric pillar and a backside surface of the second frontside gate cut dielectric pillar each extend a first width along a y-axis;
• and
• a first backside dielectric fill and a second backside dielectric fill in direct contact with the backside surface of the first frontside gate cut dielectric pillar and the backside surface of the second frontside gate cut dielectric pillar, respectively, wherein a frontside surface of the first backside dielectric fill and a frontside surface of the second backside dielectric fill each extend a second width along the y-axis, and wherein the second width is greater than the first width.

A semiconductor device comprising:

• a plurality of nanodevices including a plurality of upper transistors and a plurality of lower transistors, wherein the plurality of nanodevices include an upper active region and a lower active region that are offset from each other across the plurality of upper transistors and the plurality of lower transistors, wherein the upper active region includes an upper source/drain, and wherein the lower active region includes a lower source/drain;
• an upper source/drain contact and a lower source/drain contact connected to the upper source/drain and the lower source/drain, respectively;
• a first frontside gate cut dielectric pillar and a second frontside gate cut dielectric pillar located adjacent to and parallel to a first nanodevice and a second nanodevice, respectively, of the plurality of nanodevices along an x-axis, wherein a backside surface of the first frontside gate cut dielectric pillar and a backside surface of the second frontside gate cut dielectric pillar each extend a first width along a y-axis;
• and
• a first backside dielectric fill and a second backside dielectric fill in direct contact with the backside surface of the first frontside gate cut dielectric pillar and the backside surface of the second frontside gate cut dielectric pillar, respectively, wherein a frontside surface of the first backside dielectric fill and a frontside surface of the second backside dielectric fill each extend a second width along the y-axis, and wherein the second width is greater than the first width.