Device performance diversification

A semiconductor structure, comprising:

• a substrate;
• a first fin and a second fin rising from the substrate and spaced apart from one another by an isolation feature;
• a first leakage block layer over the first fin;
• a second leakage block layer over the second fin;
• first spacer features disposed along sidewalls of the first leakage block layer;
• second spacer features disposed along sidewalls of the second leakage block layer;
• a dielectric layer disposed over the first spacer features, the first leakage block layer and a portion of the isolation feature;
• a first source/drain feature disposed over the dielectric layer;
• and
• a second source/drain feature disposed over the second leakage block layer and the second spacer features,
• wherein the first source/drain feature is spaced apart from the first leakage block layer and the first spacer features by the dielectric layer,
• wherein the second source/drain feature is in direct contact with the second leakage block layer and the second spacer features.

A method, comprising:

• receiving a workpiece comprising:
• a fin-shaped structure extending lengthwise along a direction, the fin-shaped structure comprising bottom sacrificial layers interleaved by bottom channel layers, a middle semiconductor layer over a topmost one of the bottom channel layers, and top sacrificial layers interleaved by top channel layers,
• a dummy gate stack over a channel region of the fin-shaped structure, and
• top gate spacers disposed along sidewalls of the dummy gate stack;
• anisotropically etching a first source/drain region and a second source/drain region of the fin-shaped structure to form a first source/drain recess and a second source/drain recess, respectively, the first source/drain region and the second source/drain region sandwiching the channel region, sidewalls of the bottom channel layers and top channel layers being exposed in the first source/drain recess and the second source/drain recess;
• forming a first leakage block layer over the first source/drain recess and a second leakage block layer over the second source/drain recess;
• conformally depositing a sealing layer over dummy gate stack, the top gate spacers, the first leakage block layer, and the second leakage block layer;
• selectively removing the sealing layer over the second leakage block layer to expose the second leakage block layer;
• forming a first source/drain feature in contact with the sidewalls of the bottom channel layers and over the sealing layer;
• and
• forming a second source/drain feature in contact with the sidewalls of the bottom channel layers and over the second leakage block layer.