Thin film transistor, gate on array circuit and array substrate

A Gate on Array circuit, comprising a plurality of thin film transistors, and at least one of the thin film transistors comprising:

• a source electrode, comprising a source electrode wiring and a plurality of source electrode branches;
• a drain electrode, comprising a drain electrode wiring and a plurality of drain electrode branches;
• a gate insulated from the source electrode and the drain electrode;
• and a semiconductor layer in contact with and connected to the source electrode branch and the drain electrode branch, comprising a plurality of semiconductor branches;
• wherein the plurality of the source electrode branch, and the plurality of the drain electrode branch are in contact with the plurality of the semiconductor branch, and are divided into a plurality of cells, wherein each cell comprises M source electrode branches, N drain electrode branches and Q semiconductor branches, and M, N and Q are integers greater than or equal to 1;
• the source electrode wiring and the drain electrode wiring are arranged in parallel and spaced apart, and the number m of one of the source electrode wiring and the drain electrode wiring is an integer greater than or equal to 2, and the number n of the other is an integer greater than or equal to 1;
• multiple cells are arranged in a region between the source electrode wiring and an adjacent drain electrode wiring, and a predetermined distance is maintained between at least two of the cells;
• the number q of the cells in the thin film transistor is greater than or equal to 3;
• the first terminal of the source electrode wiring is connected to a clock pulse signal wiring, and the orthographic projection of the gate on the base substrate does not overlap with the orthographic projection of the clock pulse signal wiring on the base substrate, a gate wiring is connected to the gate, and the orthographic projection of the gate wiring on the base substrate is arranged crosswise to the orthographic projection of the clock pulse signal wiring on the base substrate.