Transistor device having gate structure with isolation region therein, and related fabrication method

A stacked field-effect transistor (FET) device comprising:

• a lower FET comprising lower channel layers and a lower gate structure that is between the lower channel layers;
• a contact that is electrically connected to the lower FET;
• an upper FET that is on top of the lower FET, the upper FET comprising upper channel layers and an upper gate structure that is between the upper channel layers, wherein the upper gate structure comprises a conductive gate and an isolation region that is between a first portion and a second portion of the conductive gate and on a sidewall of the contact;
• a spacer that separates the upper channel layers from the lower channel layers;
• and
• an insulating layer that is between a lower surface of the isolation region and an upper surface of the lower gate structure.

A method of forming a stacked field-effect transistor (FET) device, the method comprising:

• forming a nanosheet stack and a multi-layer dummy gate structure on the nanosheet stack, wherein the multi-layer dummy gate structure comprises a lower semiconductor sacrificial layer, an upper semiconductor sacrificial layer, and an etch-stop layer that is between the lower semiconductor sacrificial layer and the upper semiconductor sacrificial layer;
• etching the upper semiconductor sacrificial layer to expose sidewalls of the upper semiconductor sacrificial layer;
• forming a first insulating layer comprising vertical portions on the exposed sidewalls of the upper semiconductor sacrificial layer and a lateral portion between upper nanosheets of the nanosheet stack and lower nanosheets of the nanosheet stack;
• patterning the upper semiconductor sacrificial layer by removing a portion of the upper semiconductor sacrificial layer that is between the vertical portions of the first insulating layer and exposing an upper surface of the etch-stop layer, wherein the etch-stop layer comprises a second insulating layer;
• forming an isolation region between the vertical portions of the first insulating layer and on the exposed upper surface of the etch-stop layer;
• and
• forming a contact on a sidewall of one of the vertical portions of the first insulating layer,
• wherein the vertical portions of the first insulating layer extend longitudinally in a vertical direction that is perpendicular to the exposed upper surface of the etch-stop layer.