Back to results
US 2025/0159925 A1Published application
Memory devices including heterogeneous channels, and related electronic systems
AssigneeMicron Technology, Inc.
InventorsScott E. Sills, Ramanathan Gandhi, Durai Vishak Nirmal Ramaswamy, Yi Fang Lee, Kamal M. Karda
Life of this patent
Estimating the term…
Abstract
A transistor comprises a first conductive contact, a heterogeneous channel comprising at least one oxide semiconductor material over the first conductive contact, a second conductive contact over the heterogeneous channel, and a gate electrode laterally neighboring the heterogeneous channel. A device, a method of forming a device, a memory device, and an electronic system are also described.
Claims20
A memory device, comprising:
- an access line;
- a data line;
- a source line;
- and
- a memory cell between the data line and the source line, the memory cell comprising:
- a vertical transistor electrically coupled to the access line, the vertical transistor comprising:
- an oxide semiconductor channel comprising:
- a first region;
- a second region vertically adjacent the first region and having a larger band gap than the first region;
- a source contact vertically between the source line and the oxide semiconductor channel;
- a drain contact on the oxide semiconductor channel;
- at least one gate electrode laterally neighboring the second region of the oxide semiconductor channel and electrically coupled to the access line;
- and
- a gate dielectric material between the oxide semiconductor channel and the at least one gate electrode;
- and
- a memory element between the data line and the drain contact of the vertical transistor.
13 more elements
An electronic system, comprising:
- an input device;
- an output device;
- a processor device operably coupled to the input device and the output device;
- and
- a memory device operably coupled to the processor device and comprising at least one transistor comprising:
- a heterogeneous oxide semiconductor channel vertically between a metallic source contact and a metallic drain contact, the heterogeneous oxide semiconductor channel comprising an oxygen-rich, metal-lean middle region between at least two oxygen-lean, metal-rich end regions;
- and
- at least one gate electrode neighboring at least one side surface of the heterogeneous oxide semiconductor channel and substantially located within outermost vertical boundaries of the oxygen-rich, metal-lean middle region of the heterogeneous oxide semiconductor channel.
5 more elements
An electronic system, comprising:
- a processor device operably coupled to an input device and an output device;
- and
- a memory device operably coupled to the processor device and comprising:
- an access line;
- a data line;
- a source line;
- and
- a memory cell vertically between the data line and the source line, the memory cell comprising:
- a vertical access device comprising:
- an oxide semiconductor channel comprising:
- a first region;
- a second region vertically adjacent the first region and having a larger band gap than the first region;
- a source contact vertically between the source line and the oxide semiconductor channel;
- a drain contact on the oxide semiconductor channel;
- a gate electrode operably associated with the access line, the gate electrode vertically overlapping and horizontally neighboring the second region of the oxide semiconductor channel;
- and
- a gate dielectric material horizontally between the oxide semiconductor channel and the gate electrode;
- and
- a memory element coupled to the vertical access device and vertically positioned between the data line and the drain contact of the vertical access device.
16 more elements
Dependencies are inferred from the claim text.