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US 2025/0159893 A1Published application
Non-volatile memery cell and method of forming the same
OwnerWen-Chao SHENinventor
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Abstract
Embodiments the present disclosure provide a MTP memory cell comprising two or more bits. The memory cell includes a FinFET transistor having two or more storage nodes formed around a channel region, and two or more gate electrodes formed over the two or more storage nodes. The memory cell may be implemented by either n-channel transistor or p-channel transistor.
Claims20
A memory cell, comprising:
- a source region;
- a drain region;
- a channel region connecting the source region and the drain region, wherein the channel region has a first sidewall, a second sidewall and a top surface connecting the first sidewall and the second sidewall;
- a first gate dielectric layer disposed on the channel region;
- a storage gate electrode layer disposed on the first gate dielectric layer;
- a first control gate electrode layer disposed on the storage gate electrode layer, wherein the first gate control gate layer faces the first sidewall of the channel region;
- and
- a second control gate electrode layer disposed on the storage gate electrode layer, wherein the second gate control gate layer faces the second sidewall of the channel region, and the first control gate electrode layer and the second control gate electrode layer are electrically isolated from each other.
5 more elements
A method for operating a memory cell, comprising:
- providing a multi-time programmable memory cell comprising:
- a source region;
- a drain region;
- a channel region connected between the source region and the drain region, wherein the channel region has a first sidewall, a second sidewall and a top surface connecting the first sidewall and the second sidewall;
- a first storage node formed on the first sidewall of the channel region;
- a second storage node formed on the second sidewall of the channel region;
- a first control gate electrode layer disposed on the first storage node;
- and
- a second control gate electrode layer disposed on the second storage node;
- and
- injecting electrons to the first storage node by applying a first control voltage on the first control gate electrode layer while applying a second control voltage to the second control gate electrode layer, wherein the first control voltage is different from the second control voltage.
8 more elements
An integrated circuit, comprising:
- an array comprising a plurality of memory cells, wherein each memory cell comprising:
- a source region;
- a drain region;
- a channel region connected between the source region and the drain region, wherein the channel region has a first sidewall, a second sidewall and a top surface connecting the first sidewall and the second sidewall;
- a first storage node formed on the first sidewall of the channel region;
- a second storage node formed on the second sidewall of the channel region;
- a first control gate electrode layer disposed on the first storage node;
- and
- a second control gate electrode layer disposed on the second storage node;
- a first word line connected to the first control gate electrodes layers of the memory cells in a first row in the array;
- a second word line connected to the second control gate electrodes layers of the memory cells in the first row in the array;
- a first bit line in connection with the drain regions of a first column of memory cells in the array;
- and
- a second bit line in connection with the source regions of the first column of memory cells in the array.
11 more elements
Dependencies are inferred from the claim text.