Erasable programmable single-ploy non-volatile memory cell
AssigneeeMemory Technology Inc.
InventorHsueh-Wei CHEN
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Abstract
An erasable programmable single-poly non-volatile memory cell is provided. In the memory cell, plural doped regions are formed through different fabricating procedures. The memory cell includes a select transistor and a floating gate transistor. The channel length of the floating gate transistor is smaller than the channel length of the select transistor. The doping step in the manufacturing method is modified. Consequently, plural doped regions have different parameters and characteristics, and the channel resistance value of the floating gate transistor will be greater than that of the select transistor.
Claims20
An erasable programmable single-poly non-volatile memory cell, comprising:
- an isolation structure formed on the semiconductor substrate, wherein a surface of the semiconductor substrate is divided into a first region and a second region by the isolation structure;
- a first well region formed in the surface of the semiconductor substrate corresponding to the first region;
- a second well region formed in the surface of the semiconductor substrate corresponding to the second region;
- a first gate structure and a second gate structure formed on the surface of the semiconductor substrate corresponding to the first region, wherein an area in the surface of the semiconductor substrate corresponding to the first region is divided into a first merged doped region, a second merged doped region and a third merged doped region by the first gate structure and a second gate structure;
- and
- a fourth merged doped region formed in the surface of the semiconductor substrate corresponding to the second region and located beside a side of the second gate structure,
- wherein the first merged doped region is located beside a first side of the first gate structure, the second merged doped region is arranged between a second side of the first gate structure and a first side of the second gate structure, and the third merged doped region is located beside a second side of the second gate structure,
- wherein the second gate structure is externally extended to the second region through a surface of the isolation structure, and a portion of the second region is covered by the second gate structure,
- wherein the first merged doped region, the first gate structure and the second merged doped region are collaboratively formed as a select transistor, the second merged doped region, the second gate structure and the third merged doped region are collaboratively formed as a floating gate transistor, and the second gate structure and the fourth merged doped region are collaboratively formed as a first MOS capacitor, wherein a channel resistance value of the floating gate transistor is greater than a channel resistance value of the select transistor.
Dependencies are inferred from the claim text.