Vertical gate dram device

A semiconductor device, comprising:

• at least one vertical pillar, the at least one vertical pillar has a first end and a second end opposite to the first end;
• at least one gate line on a gate dielectric layer formed on sidewalls of the at least one vertical pillar;
• a first p-type region at the first end of the at least one vertical pillar;
• a storage unit connects with the first p-type region;
• a second p-type region at the second end of the at least one vertical pillar, the second p-type region comprises at least p-type silicon germanium (SiGe);
• and
• a bit line in connection with the second p-type region at the second end of the at least one vertical pillar.

A memory system, comprising:

• a semiconductor device configured to store data, and comprising:
• at least one vertical pillar, the at least one vertical pillar has a first end and a second end opposite to the first end;
• at least one gate line on a gate dielectric layer formed on sidewalls of the at least one vertical pillar;
• a first p-type region at the first end of the at least one vertical pillar;
• a storage unit connects with the first p-type region;
• a second p-type region at the second end of the at least one vertical pillar, the second p-type region comprises at least p-type silicon germanium (SiGe);
• and
• a bit line in connection with the second p-type region at the second end of the at least one vertical pillar;
• and
• a memory controller coupled to the semiconductor device and configured to control the semiconductor device through the at least one gate line and the bit line.