Three-dimensional semiconductor devices

A semiconductor device, comprising:

• bit lines disposed on a substrate, each of the bit lines extending primarily in a first direction, and the bit lines being spaced apart from each other in a second direction that is perpendicular to the first direction;
• a first transistor, a capacitor and a second transistor sequentially disposed in the second direction between the bit lines;
• and
• a word line including:
• first extension portions electrically connected to the first and second transistor, respectively, each of the first extension portions extending primarily in a third direction that is perpendicular to the first and second directions;
• and
• a second extension portion extending primarily in the second direction and being connected to the first extension portions,
• wherein each of the first and second transistors includes:
• a gate electrode electrically connected to each of the first extension portions of the word line;
• a channel electrically connected to the gate electrode;
• and
• first and second source/drain layers disposed at opposite sides, respectively, of the channel in the second direction,
• wherein the capacitor includes a first capacitor electrode, a dielectric pattern and a second capacitor electrode sequentially stacked, and
• wherein the first source/drain layers of the first and second transistors, respectively, are electrically connected to the bit lines, respectively, and the second source/drain layers of the first and second transistors, respectively, are electrically connected to the first and second capacitor electrodes, respectively.

A semiconductor device, comprising:

• first and second bit lines on a substrate, each of the first and second bit lines extending primarily in a first direction that is perpendicular to an upper surface of the substrate, and the first and second bit lines being spaced apart from each other in a second direction that is parallel to the upper surface of the substrate;
• a word line including:
• first extension portions between the first and second bit lines, each of the first extension portions extending primarily in a third direction that is parallel to the upper surface of the substrate and intersecting the second direction;
• and
• a second extension portion extending primarily in the second direction at the same level as the first extension portions and being connected to the first extension portions;
• first and second channels each extending through the first extension portions of the word line;
• a first source/drain layer disposed between and contacting both the first bit line and the first channel;
• a second source/drain layer disposed between and contacting both the second bit line and the second channel;
• a capacitor including:
• a first capacitor electrode contacting the first source/drain layer;
• a dielectric pattern disposed on a surface of the first capacitor electrode;
• and
• a second capacitor electrode disposed on a surface of the dielectric pattern;
• a third source/drain layer disposed between and contacting both the first channel and the first capacitor electrode;
• a fourth source/drain layer disposed between the second channel and the second capacitor electrode;
• a connection pattern contacting both the second capacitor electrode and the second source/drain layer;
• and
• an insulation pattern disposed between the first capacitor electrode and the connection pattern.