US 2025/0159855 A1Published application

Memory device and method for driving memory device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsTakeya HIROSE, Takanori MATSUZAKI

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Abstract

A novel semiconductor device is provided. One of a source and a drain of a first transistor is connected to one terminal of a first capacitor; the other of the source and the drain of the first transistor is connected to a bit line; a gate of the first transistor is connected to a word line; the other terminal of the first capacitor is connected to a first driver circuit; the first driver circuit is configured to output a first potential, output a second potential in conjunction with a timing when a potential of a selection signal that is supplied to the word line changes, and output a third potential in conjunction with a timing when a potential of data that is supplied to the bit line changes; a direction of change from the first potential to the second potential is opposite to a direction in which the potential of the selection signal changes; and a direction of change from the first potential to the third potential is opposite to a direction in which the potential of the data changes.

Claims20

Dependent claims

A memory device comprising:

a memory array comprising a first memory cell;
and
a peripheral circuit comprising a first driver circuit,
wherein the first memory cell comprises a first transistor and a first capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first bit line,
wherein a gate of the first transistor is electrically connected to a first word line,
wherein the other terminal of the first capacitor is electrically connected to the first driver circuit,
wherein the first driver circuit is configured to output a first potential, output a second potential in conjunction with a timing when a potential of a selection signal that is supplied to the first word line changes, and output a third potential in conjunction with a timing when a potential of data that is supplied to the first bit line changes,
wherein a direction of change from the first potential to the second potential is opposite to a direction in which the potential of the selection signal changes, and
wherein a direction of change from the first potential to the third potential is opposite to a direction in which the potential of the data changes.

8 more elements

A memory device comprising:

a memory array comprising a first memory cell and a second memory cell;
and
a peripheral circuit comprising a first driver circuit and a second driver circuit,
wherein the first memory cell comprises a first transistor and a first capacitor,
wherein the second memory cell comprises a second transistor and a second capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first bit line,
wherein a gate of the first transistor is electrically connected to a first word line,
wherein the other terminal of the first capacitor is electrically connected to the first driver circuit,
wherein one of a source and a drain of the second transistor is electrically connected to one terminal of the second capacitor,
wherein the other of the source and the drain of the second transistor is electrically connected to the first bit line,
wherein a gate of the second transistor is electrically connected to a second word line,
wherein the other terminal of the second capacitor is electrically connected to the second driver circuit,
wherein the first driver circuit is configured to output a signal whose potential changes in a direction opposite to a direction in which a potential of a selection signal that is supplied to the first word line changes, and
wherein the second driver circuit is configured to output a signal whose potential changes in a direction opposite to a direction in which a potential of a selection signal that is supplied to the second word line changes.

12 more elements

A memory device comprising:

a memory array comprising a first memory cell and a second memory cell;
and
a peripheral circuit comprising a first driver circuit and a second driver circuit,
wherein the first memory cell comprises a first transistor and a first capacitor,
wherein the second memory cell comprises a second transistor and a second capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first bit line,
wherein a gate of the first transistor is electrically connected to a first word line,
wherein the other terminal of the first capacitor is electrically connected to the first driver circuit,
wherein one of a source and a drain of the second transistor is electrically connected to one terminal of the second capacitor,
wherein the other of the source and the drain of the second transistor is electrically connected to a second bit line,
wherein a gate of the second transistor is electrically connected to the first word line,
wherein the other terminal of the second capacitor is electrically connected to the second driver circuit,
wherein the first driver circuit is configured to output a signal whose potential changes in a direction opposite to a direction in which a potential of data that is supplied to the first bit line changes, and
wherein the second driver circuit is configured to output a signal whose potential changes in a direction opposite to a direction in which a potential of data that is supplied to the second bit line changes.

12 more elements

A memory device comprising:

a memory array comprising a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell;
and
a peripheral circuit comprising a first driver circuit, a second driver circuit, a third driver circuit, and a fourth driver circuit,
wherein the first memory cell comprises a first transistor and a first capacitor,
wherein the second memory cell comprises a second transistor and a second capacitor,
wherein the third memory cell comprises a third transistor and a third capacitor,
wherein the fourth memory cell comprises a fourth transistor and a fourth capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first bit line,
wherein a gate of the first transistor is electrically connected to a first word line,
wherein the other terminal of the first capacitor is electrically connected to the first driver circuit,
wherein one of a source and a drain of the second transistor is electrically connected to one terminal of the second capacitor,
wherein the other of the source and the drain of the second transistor is electrically connected to the first bit line,
wherein a gate of the second transistor is electrically connected to a second word line,
wherein the other terminal of the second capacitor is electrically connected to the second driver circuit,
wherein one of a source and a drain of the third transistor is electrically connected to one terminal of the third capacitor,
wherein the other of the source and the drain of the third transistor is electrically connected to a second bit line,
wherein a gate of the third transistor is electrically connected to the first word line,
wherein the other terminal of the third capacitor is electrically connected to the third driver circuit,
wherein one of a source and a drain of the fourth transistor is electrically connected to one terminal of the fourth capacitor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the second bit line,
wherein a gate of the fourth transistor is electrically connected to the second word line, and
wherein the other terminal of the fourth capacitor is electrically connected to the fourth driver circuit.

20 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/928,345Filed 28 Oct 2024
Priority: JP 2023-19240310 Nov 2023
Published: 15 May 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
H10B 12/50
Dynamic random access memory [DRAM] devices: peripheral circuit region structures
G11C 11/404
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with one charge-transfer gate, e.g. MOS transistor, per cell
H10B 10/18
Static random access memory [SRAM] devices: peripheral circuit regions

Family

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