Level shifter

A level shifter for converting an input signal between a first supply voltage and a ground voltage into an output signal between a second supply voltage and the ground voltage, the level shifter comprising:

• a first load circuit, wherein a first terminal of the first load circuit receives the second supply voltage;
• a second load circuit, wherein a first terminal of the second load circuit receives the input signal;
• y BJT transistors, wherein bases of the y BJT transistors are connected with the second load circuit, and y is an integer greater than or equal to 1, wherein in the y BJT transistors, a collector of a first BJT transistor is connected with a second terminal of the first load circuit, an emitter of a y-th BJT transistor is connected with a first node, a collector of each of the other BJT transistors is connected with an emitter of a previous BJT transistor, and an emitter of each of the other BJT transistors is connected with a collector of a next BJT transistor;
• z MOSFET transistors, wherein gate terminals of the z MOSFET transistors receive the input signal, z is an integer greater than or equal to 1, and if one of y and z is 1, the other of y and z is not 1, wherein in the z MOSFET transistors, a drain terminal of a first MOSFET transistor is connected with the first node, a source terminal of a z-th MOSFET transistor receives the ground voltage, a drain terminal of each of the other MOSFET transistors is connected with a source terminal of a previous MOSFET transistor, and a source terminal of each of the other MOSFET transistor is connected with a drain terminal of a next MOSFET transistor;
• and
• a NOT gate, wherein a first power terminal of the NOT gate receives the second supply voltage, a second power terminal of the NOT gate receives the ground voltage, an input terminal of the NOT gate is connected with the first load circuit, and an output terminal of the NOT gate generates the output signal.

A level shifter for converting an input signal and an inverted input voltage between a first supply voltage and a ground voltage into an output signal between a second supply voltage and the ground voltage, the level shifter comprising:

• a first load circuit, wherein the first load circuit is connected with the second supply voltage, a first node and a second node, and a voltage at the second node is the output signal;
• a second load circuit, wherein a first terminal of the second load circuit receives the input signal;
• a third load circuit, wherein a first terminal of the third load circuit receives the inverted input signal;
• a first BJT transistor, wherein a collector of the first BJT transistor is connected with the first node, and a base of the first BJT transistor is connected with a second terminal of the second load circuit;
• a second BJT transistor, wherein a collector of the second BJT transistor is connected with the second node, and a base of the second BJT transistor is connected with a second terminal of the third load circuit;
• a first MOSFET transistor, wherein a drain terminal of the first MOSFET transistor is connected with an emitter of the first BJT transistor, a source terminal of the first MOSFET transistor receives the ground voltage, and a gate terminal of the first MOSFET transistor receives the input signal;
• and
• a second MOSFET transistor, wherein a drain terminal of the second MOSFET transistor is connected with an emitter of the second BJT transistor, a source terminal of the second MOSFET transistor receives the ground voltage, and a gate terminal of the second MOSFET transistor receives the inverted input signal.

A level shifter for converting an input signal and an inverted input voltage between a first supply voltage and a ground voltage into an output signal between a second supply voltage and the ground voltage, the level shifter comprising:

• a first load circuit, wherein the first load circuit is connected with the second supply voltage, a first node and a second node, and a voltage at the second node is the output signal;
• a second load circuit, wherein a first terminal of the second load circuit receives the input signal;
• a third load circuit, wherein a first terminal of the third load circuit receives the inverted input signal;
• a first group of y BJT transistors, wherein bases of the first group of y BJT transistors are connected with the second load circuit, and y is an integer greater than or equal to 1, wherein in the first group of y BJT transistors, a collector of a first BJT transistor is connected with the first node, an emitter of a y-th BJT transistor is connected with a third node, a collector of each of the other BJT transistors is connected with an emitter of a previous BJT transistor, and an emitter of each of the other BJT transistors is connected with a collector of a next BJT transistor;
• a second group of y BJT transistors, wherein bases of the second group of y BJT transistors are connected with the third load circuit, wherein in the second group of y BJT transistors, a collector of a first BJT transistor is connected with the second node, an emitter of a y-th BJT transistor is connected with a fourth node, a collector of each of the other BJT transistors is connected with an emitter of a previous BJT transistor, and an emitter of each of the other BJT transistors is connected with a collector of a next BJT transistor;
• a third group of z MOSFET transistors, wherein gate terminals of the third group of z MOSFET transistors receive the input signal, z is an integer greater than or equal to 1, and if one of y and z is 1, the other of y and z is not 1, wherein in the third group of z MOSFET transistors, a drain terminal of a first MOSFET transistor is connected with the third node, a source terminal of a z-th MOSFET transistor receives the ground voltage, a drain terminal of each of the other MOSFET transistors is connected with a source terminal of a previous MOSFET transistor, and a source terminal of each of the other MOSFET transistor is connected with a drain terminal of a next MOSFET transistor;
• and
• a fourth group of z MOSFET transistors, wherein gate terminals of the fourth group of z MOSFET transistors receive the inverted input signal, wherein in the fourth group of z MOSFET transistors, a drain terminal of a first MOSFET transistor is connected with the fourth node, a source terminal of a z-th MOSFET transistor receives the ground voltage, a drain terminal of each of the other MOSFET transistors is connected with a source terminal of a previous MOSFET transistor, and a source terminal of each of the other MOSFET transistor is connected with a drain terminal of a next MOSFET transistor.