Logic chip, memory chip, chip stack structure, and memory

A memory chip, comprising m channels sequentially arranged along a first direction, wherein the memory chip has a chip axis extending along a second direction and passing through a center of the memory chip, and the m channels are arranged symmetrically about the chip axis;

• each one of the channels comprises a first memory array region, a channel signal region, and a second memory array region sequentially arranged along the second direction, a center of each one of the channel signal regions is coincident with a center of a corresponding channel thereof, and m is a positive integer;
• each one of the channel signal regions has a first axis and a second axis, wherein the first axis extends along the first direction or the second direction, and the second axis and the first axis are perpendicular to each other and intersect at a center of a corresponding channel signal region thereof;
• each one of the channel signal regions is penetrated through by a plurality of conductive vias along a third direction, any two of the first direction, the second direction, and the third direction are perpendicular to each other, the first direction and the second direction are parallel to a top surface of the memory chip, and the third direction is perpendicular to the top surface of the memory chip;
• for each one of the channel signal regions, the plurality of conductive vias therein are divided into a plurality of repair unit groups;
• each one of the plurality of repair unit groups comprises a first repair unit, a second repair unit, a third repair unit, and a fourth repair unit;
• the first repair unit and the second repair unit are arranged symmetrically about the first axis of a corresponding channel signal region thereof, the third repair unit and the fourth repair unit are arranged symmetrically about the first axis of a corresponding channel signal region thereof, and the first repair unit and the fourth repair unit are arranged symmetrically about the second axis of a corresponding channel signal region thereof;
• each one of the repair units comprises at least one redundant conductive via and at least one normal conductive via, and in a case that any one of the at least one normal conductive via is damaged, an effective signal transmitted by the normal conductive via is switched to a next conductive via in a same one of the repair units along a preset switching direction;
• any one of the conductive vias in the first repair unit is electrically connected to an internal circuit of the memory chip when used for transmitting an effective signal;
• the normal conductive via in the first repair unit and the normal conductive via in the second repair unit are in one-to-one correspondence and are arranged symmetrically about the first axis of a corresponding channel signal region thereof, the normal conductive via in the third repair unit and the normal conductive via in the fourth repair unit are in one-to-one correspondence and are arranged symmetrically about the first axis of a corresponding channel signal region thereof, and the normal conductive via in the first repair unit and the normal conductive via in the fourth repair unit are in one-to-one correspondence and are arranged symmetrically about the second axis of a corresponding channel signal region thereof.