Semiconductor package

A semiconductor package, comprising:

• a first semiconductor chip;
• and
• a second semiconductor chip on the first semiconductor chip,
• wherein an upper portion of the first semiconductor chip comprises upper bonding pads,
• wherein a lower portion of the second semiconductor chip comprises lower bonding pads that are in direct contact with the upper bonding pads,
• wherein the first semiconductor chip and the second semiconductor chip are connected to each other by the upper bonding pads and the lower bonding pads,
• wherein the upper bonding pads comprise a first pad, a dummy pad, and a second pad, which are arranged in a first direction,
• wherein the first pad is adjacent to the dummy pad and the dummy pad is adjacent to the second pad, such that the dummy pad is in between the first pad and the second pad, and
• wherein the first pad is configured to be applied with a first power voltage,
• wherein the second pad is configured to be applied with one from among a second power voltage, a ground voltage, and a signal voltage,
• wherein a voltage level of the one from among the second power voltage, the ground voltage, and the signal voltage is greater than a voltage level of the first power voltage, and
• wherein the dummy pad is configured to be applied with a floating voltage.

A semiconductor package, comprising:

• a package substrate;
• an interposer on the package substrate;
• a logic chip on the interposer;
• and
• a plurality of chip stacks, which are spaced apart from each other with the logic chip interposed therebetween,
• wherein each of the plurality of chip stacks comprises:
• a first semiconductor chip;
• and
• a second semiconductor chip on the first semiconductor chip,
• wherein the first semiconductor chip comprises an upper insulating layer at an upper level of the first semiconductor chip, uppermost metal lines in the upper insulating layer, and upper bonding pads on the uppermost metal lines,
• wherein the second semiconductor chip comprises a lower insulating layer at a lower level of the second semiconductor chip, and lower bonding pads in the lower insulating layer, the lower bonding pads being in direct contact with the upper bonding pads of the first semiconductor chip,
• wherein the first semiconductor chip and the second semiconductor are bonded to each other through the upper bonding pads and the lower bonding pads,
• wherein the upper bonding pads comprise a ground pad, a first power pad, a signal pad, and a first dummy pad,
• wherein the first dummy pad is between one from among the signal pad and the ground pad and the first power pad, and
• wherein the first dummy pad is disposed adjacent to the one from among the signal pad and the ground pad, and adjacent to the first power pad.