Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsSangho CHA, Yun-Rae Cho
Life of this patent
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Abstract
A semiconductor package includes: a first semiconductor chip having a first region and a second region contacting the first region; and a second semiconductor chip on a top surface of the first semiconductor chip, wherein the first semiconductor chip includes: a first pad in the first region and on the top surface of the first semiconductor chip, the first pad comprising a first pad portion and a first protrusion protruding from a top surface of the first pad portion; and a second pad in the second region and on the top surface of the first semiconductor chip and having a flat top surface.
Claims20
A semiconductor package comprising:
- a first semiconductor chip having a first region and a second region contacting the first region;
- a second semiconductor chip on a top surface of the first semiconductor chip;
- a first connection terminal;
- and
- a second connection terminal,
- wherein the first semiconductor chip comprises:
- a first pad in the first region and on the top surface of the first semiconductor chip, the first pad comprising a first pad portion and a first protrusion protruding from a top surface of the first pad portion;
- and
- a second pad in the second region and on the top surface of the first semiconductor chip, the second pad having a flat top surface,
- wherein the second semiconductor chip comprises:
- a third pad in the first region and on a bottom surface of the second semiconductor chip;
- and
- a fourth pad in the second region and on the bottom surface of the second semiconductor chip,
- wherein the first pad and the third pad are connected to each other through the first connection terminal, and
- wherein the second pad and the fourth pad are connected to each other through the second connection terminal.
A semiconductor package comprising:
- a substrate having a first region and a second region;
- a base chip on the substrate;
- second semiconductor chips stacked on a top surface of the base chip;
- a substrate connection terminal on a bottom surface of the substrate;
- and
- a molding layer surrounding the base chip and the second semiconductor chips on the substrate,
- wherein the substrate comprises:
- a first pad disposed on a top surface of the substrate of the first region;
- a protrusion disposed on a top surface of the first pad;
- and
- a second pad disposed on the top surface of the substrate of the second region,
- wherein a width of the protrusion is less than a width of the first pad,
- wherein the base chip is electrically connected to the substrate through a connection terminal provided on a bottom surface of the base chip, and
- wherein a distance between the top surface of the substrate and the bottom surface of the base chip on the first region is greater than a distance between the top surface of the substrate and the bottom surface of the base chip on the second region.
A semiconductor package comprising:
- a first semiconductor chip having a central region and a peripheral region surrounding the central region in a plan view;
- and
- a second semiconductor chip on a top surface of the first semiconductor chip,
- wherein the first semiconductor chip comprises a first pad on the top surface of the first semiconductor chip and a second pad on the top surface of the first semiconductor chip,
- wherein the first pad comprises at least one protrusion on a top surface of the first pad,
- wherein a height of the first pad is greater than a height of the second pad,
- wherein one of the first pad and the second pad is in the central region and on the top surface of the first semiconductor chip, and
- wherein the other one of the first pad and the second pad is in the peripheral region and on the top surface of the first semiconductor chip.
Dependencies are inferred from the claim text.