Semiconductor package

A semiconductor package, comprising:

• a first semiconductor chip comprising a first substrate having a first front surface and a first rear surface opposite to each other, a plurality of first rear pads on the first rear surface, a first passivation layer on at least a portion of each of the plurality of first rear pads, and a plurality of first through-electrodes penetrating through the first substrate and electrically connected to the plurality of first rear pads;
• a second semiconductor chip comprising a second substrate having a second front surface and a second rear surface opposite to each other, a plurality of first front pads on the second front surface and in contact with the plurality of first rear pads, a plurality of second rear pads on the second rear surface, a second passivation layer on at least a portion of each of the plurality of second rear pads, and a plurality of second through-electrodes penetrating through the second substrate and electrically connected to the plurality of second rear pads;
• a first sealing layer comprising a gap-fill portion on a side surface of the second semiconductor chip and at least a portion of each of the plurality of first front pads, and a passivation portion on the gap-fill portion and in contact with the first passivation layer;
• at least one third semiconductor chip comprising a third substrate having a third front surface and a third rear surface opposite to each other, a plurality of second front pads on the third front surface and in contact with the plurality of second rear pads, a third passivation layer on at least a portion of each of the plurality of second front pads and in contact with the second passivation layer, a plurality of third rear pads on the third rear surface, and a plurality of third through-electrodes penetrating through the third substrate and electrically connected to the plurality of third rear pads;
• a second sealing layer on a side surface of the at least one third semiconductor chip, and on at least a portion of each of the plurality of third rear pads;
• a plurality of first through-vias penetrating through the first sealing layer and electrically connected to at least some of the plurality of first rear pads;
• a plurality of second through-vias penetrating through the second sealing layer and electrically connected to the plurality of first through-vias;
• and
• a plurality of connection bumps on the plurality of third rear pads and the plurality of second through-vias,
• wherein a material of the first sealing layer is different from a material of the second sealing layer.

A semiconductor package, comprising:

• a first semiconductor chip comprising a plurality of first rear pads, and a plurality of first through-electrodes electrically connected to the plurality of first rear pads;
• a second semiconductor chip comprising a plurality of first front pads in contact with the plurality of first rear pads, a plurality of second rear pads, and a plurality of second through-electrodes electrically connected to the plurality of second rear pads;
• at least one third semiconductor chip comprising a plurality of second front pads in contact with the plurality of second rear pads, a plurality of third rear pads, and a plurality of third through-electrodes electrically connected to the plurality of third rear pads;
• a plurality of first through-vias on at least one side of the second semiconductor chip and electrically connected to at least some of the plurality of first rear pads;
• a plurality of second through-vias on at least one side of the at least one third semiconductor chip and electrically connected to the plurality of first through-vias;
• and
• a plurality of connection bumps on the plurality of third rear pads and the plurality of second through-vias,
• wherein the first semiconductor chip is configured to receive power through the plurality of first through-vias and the plurality of second through-vias, and
• wherein the second semiconductor chip is configured to receive power through the plurality of third through-electrodes of the at least one third semiconductor chip.