Multilayer ceramic electronic component and mounting structure of multilayer ceramic electronic component

A multilayer ceramic electronic component comprising:

• a multilayer body including a plurality of stacked ceramic layers, a first main surface and a second main surface facing each other in a height direction, a first end surface and a second end surface facing each other in a length direction orthogonal or substantially orthogonal to the height direction, and a first side surface and a second side surface facing each other in a width direction orthogonal or substantially orthogonal to the height direction and the length direction;
• a plurality of first inner electrode layers on the plurality of ceramic layers and extending to the first end surface and the second end surface;
• a plurality of second inner electrode layers on the plurality of ceramic layers and extending to the first side surface and the second side surface;
• a first outer electrode on the first end surface, extending from the first end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and being connected to the first inner electrode layers;
• a second outer electrode on the second end surface, extending from the second end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and being connected to the first inner electrode layers;
• a third outer electrode on the first side surface, extending from the first side surface to a portion of the first main surface and a portion of the second main surface, and being connected to the second inner electrode layers;
• and
• a fourth outer electrode on the second side surface, extending from the second side surface to a portion of the first main surface and a portion of the second main surface, and being connected to the second inner electrode layers;
• wherein
• the first outer electrode includes a first base electrode layer on the multilayer body, a first lower plating layer on the first base electrode layer, and a first upper plating layer on the first lower plating layer except for a first plating exposed region exposed on a surface of the first outer electrode so that the first lower plating layer includes the first plating exposed region;
• the second outer electrode includes a second base electrode layer on the multilayer body, a second lower plating layer on the second base electrode layer, and a second upper plating layer on the second lower plating layer except for a second plating exposed region exposed on a surface of the second outer electrode so that the second lower plating layer has the second plating exposed region;
• the third outer electrode includes a third base electrode layer on the multilayer body, a third lower plating layer on the third base electrode layer, and a third upper plating layer on the third lower plating layer;
• and
• the fourth outer electrode includes a fourth base electrode layer on the multilayer body, a fourth lower plating layer on the fourth base electrode layer, and a fourth upper plating layer on the fourth lower plating layer.

A multilayer ceramic electronic component comprising:

• a multilayer body including a plurality of stacked ceramic layers, a first main surface and a second main surface facing each other in a height direction, a first end surface and a second end surface facing each other in a length direction orthogonal or substantially orthogonal to the height direction, and a first side surface and a second side surface facing each other in a width direction orthogonal or substantially orthogonal to the height direction and the length direction;
• a plurality of first inner electrode layers on the plurality of ceramic layers and extending to the first end surface and the second end surface;
• a plurality of second inner electrode layers on the plurality of ceramic layers and extending to the first side surface and the second side surface;
• a first outer electrode on the first end surface, extending from the first end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and being connected to the first inner electrode layers;
• a second outer electrode on the second end surface, extending from the second end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and being connected to the first inner electrode layers;
• a third outer electrode on the first side surface, extending from the first side surface to a portion of the first main surface and a portion of the second main surface, and being connected to the second inner electrode layers;
• and
• a fourth outer electrode on the second side surface, extending from the second side surface to a portion of the first main surface and a portion of the second main surface, and being connected to the second inner electrode layers;
• wherein
• the first outer electrode includes a first base electrode layer on the multilayer body, a first lower plating layer on the first base electrode layer, and a first upper plating layer on the first lower plating layer;
• the second outer electrode includes a second base electrode layer on the multilayer body, a second lower plating layer on the second base electrode layer, and a second upper plating layer on the second lower plating layer;
• the third outer electrode includes a third base electrode layer on the multilayer body, a third lower plating layer on the third base electrode layer, and a third upper plating layer on the third lower plating layer except for a third plating exposed region exposed on a surface of the third outer electrode so that the third lower plating layer includes the third plating exposed region;
• and
• the fourth outer electrode includes a fourth base electrode layer on the multilayer body, a fourth lower plating layer on the fourth base electrode layer, and a fourth upper plating layer on the fourth lower plating layer except for a fourth plating exposed region exposed on a surface of the fourth outer electrode so that the fourth lower plating layer includes the fourth plating exposed region.