US 2025/0157564 A1 · MEMORY SYSTEM AND METHOD

Abstract

A memory system includes a semiconductor memory device including a plurality of memory cells each configured to store data in a non-volatile manner according to a threshold voltage thereof and connected to a word line, and a controller configured to perform an error correction based on hard bit data and soft bit data read from the plurality of memory cells, generate a first table based on corrected data, determine a voltage difference between a first voltage and a second voltage, the first voltage being a voltage applied to the word line when the data being corrected is read, and correct the first table based on the voltage difference.

Claims20

Dependent claims

A memory system comprising:

a semiconductor memory device including a plurality of memory cells each configured to store data in a non-volatile manner according to a threshold voltage thereof and connected to a first word line;
and
a controller configured to:
perform an error correction to correct first data read from the plurality of memory cells and obtain second data;
generate a first table based on the second data obtained by the error correction;
determine a voltage difference between a first voltage and a second voltage, the first voltage being a voltage applied to the first word line when the first data was read;
and
correct the generated first table based on the voltage difference.

5 more elements

A method of controlling a plurality of memory cells each configured to store data in a non-volatile manner according to a threshold voltage thereof, the plurality of memory cells including at least first memory cells connected to a first word line, said method comprising:

performing a first error correction to correct first data read from the first memory cells and obtain second data;
generating a first table based on the second data obtained by the first error correction;
determining a voltage difference between a first voltage and a second voltage, the first voltage being a voltage applied to the first word line when the first data was acquired;
and
correcting the generated first table based on the voltage difference.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

19/021,029Filed 14 Jan 2025

Priority

JP 2022-04399518 Mar 2022

Published

15 May 2025

Term ends

Not estimatedThe source records don’t support an estimate.

Classification20 codes

G11C 29/52
Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation: protection of memory contents;…
G06F 11/10
Error detection or correction by redundancy in data representation, e.g. by using checking codes: adding special bits or symbols to the coded…
G06F 11/1068
In individual solid state devices: in sector programmable memories, e.g. flash disk
G11C 8/08
Arrangements for selecting an address in a digital store: word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down…

Memory system and method

Life of this patent

Memory system and method

Life of this patent

Abstract

Claims20