Erase verify mode to reduce power consumption in erase operation of non-volatile memory apparatus

A controller in communication with a memory apparatus including memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage and disposed in memory holes each defining a channel, the memory holes grouped into a plurality of strings, the controller configured to:

• instruct the memory apparatus to apply at least one erase pulse to the channel of the memory holes of all of the plurality of strings;
• and
• instruct the memory apparatus to apply an erase verify voltage to the plurality of word lines and successively determine whether at least some of the memory cells of ones of the plurality of strings being erased have the threshold voltage below the erase verify voltage in a plurality of subsequent erase verify iterations, the application of the erase verify voltage to the plurality of word lines maintained constantly throughout an entire duration of the plurality of subsequent erase verify iterations for the at least some of the memory cells.

A method of operating a memory apparatus including memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage and disposed in memory holes each defining a channel, the memory holes grouped into a plurality of strings, the method comprising the steps of:

• applying at least one erase pulse to the channel of the memory holes of all of the plurality of strings;
• and
• applying an erase verify voltage to the plurality of word lines and successively determining whether at least some of the memory cells of ones of the plurality of strings being erased have the threshold voltage below the erase verify voltage in a plurality of subsequent erase verify iterations, the application of the erase verify voltage to the plurality of word lines maintained constantly throughout an entire duration of the plurality of subsequent erase verify iterations for the at least some of the memory cells.