US 2025/0157540 A1 · VARIABLE FOGGY VERIFY LEVELS FOR SELECTED CHECKPOINT STATES FOR NON-VOLATILE MEMORY APPARATUSES

Abstract

A memory apparatus includes memory cells and a control means configured to adjust at least one of blind program pulses applied to word lines connected to the memory cells and bit line voltages applied to bit lines coupled to the memory cells in response to determining one of the word lines connected to the memory cells being programmed is susceptible to over-programming. The control means programs non-checkpoint ones of the memory cells associated with a checkpoint state to a verify low voltage for the checkpoint state and programs the non-checkpoint ones of the memory cells to respective non-checkpoint states associated with the checkpoint state by applying the blind program pulses to each non-checkpoint one of the memory cells without verifying whether the non-checkpoint ones of the memory cells have reached their respective non-checkpoint states while applying the bit line voltages to the bit lines associated therewith.

Claims20

Dependent claims

A memory apparatus, comprising:

memory cells;
and
a control means configured to:
adjust at least one of blind program pulses applied to word lines connected to the memory cells and bit line voltages applied to bit lines coupled to the memory cells and a verify low voltage for a checkpoint state in response to determining the one of the word lines is susceptible to over-programming, and
program non-checkpoint ones of the memory cells to the verify low voltage and continue programming by applying the blind program pulses to the non-checkpoint ones of the memory cells without verifying while applying the bit line voltages to the bit lines coupled thereto.

2 more elements

A controller in communication with a memory apparatus including memory cells, the controller configured to:

instruct the memory apparatus to adjust at least one of blind program pulses applied to one of a word lines connected to the memory cells and bit line voltages applied to bit lines coupled to the memory cells and a verify low voltage for a checkpoint state in response to determining the one of the word lines is susceptible to over-programming;
and
instruct the memory apparatus to program non-checkpoint ones of the memory cells to the verify low voltage and continue programming by applying the blind program pulses to the non-checkpoint ones of the memory cells without verifying while applying the bit line voltages to the bit lines coupled thereto.

A method of operating a memory apparatus including memory cells, the method comprising the steps of:

adjusting at least one of blind program pulses applied to word lines connected to the memory cells and bit line voltages applied to bit lines coupled to the memory cells and a verify low voltage for a checkpoint state in response to determining the one of the word lines is susceptible to over-programming;
and
programing non-checkpoint ones of the memory cells to the verify low voltage and continue programming by applying the blind program pulses to the non-checkpoint ones of the memory cells without verifying while applying the bit line voltages to the bit lines coupled thereto.

Dependencies are inferred from the claim text.

Variable foggy verify levels for selected checkpoint states for non-volatile memory apparatuses

Life of this patent

Variable foggy verify levels for selected checkpoint states for non-volatile memory apparatuses

Life of this patent

Abstract

Claims20