US 2025/0157535 A1 · METHOD FOR OPERATING MEMORY APPARATUS, MEMORY APPARATUS, DEVICE, AND STORAGE MEDIUM

Abstract

A method for operating a memory apparatus, a memory apparatus, a device, and a storage medium are provided. The method includes: providing a semiconductor device including a substrate, a deep N-well region disposed in the substrate, a P-well region disposed in the deep N-well region, and a plurality of transistor structures disposed in the P-well region, where each of the transistor structures includes a gate, a source and a drain; and applying a first voltage to a port of the gate, a second voltage to a port of the deep N-well region, and a third voltage to a port of the P-well region. When a first operation is performed, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a negative voltage; when a second operation is performed, the first, second and third voltages are positive voltages.

Claims12

Dependent claims

A method for operating a memory apparatus, comprising:

providing a semiconductor device, wherein the semiconductor device comprises a substrate, a deep N-well region disposed in the substrate, a P-well region disposed in the deep N-well region, and a plurality of transistor structures disposed in the P-well region;
wherein each of the plurality of transistor structures comprises a gate, as well as a source and a drain disposed on two sides of the gate respectively;
and
applying a first voltage to a port of the gate, applying a second voltage to a port of the deep N-well region, and applying a third voltage to a port of the P-well region;
wherein when a first operation is performed, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a negative voltage;
when a second operation is performed, the first voltage is a positive voltage, the second voltage is a positive voltage, and the third voltage is a positive voltage.

3 more elements

A memory apparatus, comprising:

a semiconductor device;
wherein the semiconductor device comprises a substrate, a deep N-well region disposed in the substrate, a P-well region disposed in the deep N-well region, and a plurality of transistor structures disposed in the P-well region;
wherein each of the plurality of transistor structures comprises a gate, as well as a source and a drain disposed on two sides of the gate respectively;
and
a voltage module, configured to apply a first voltage to a port of the gate, apply a second voltage to a port of the deep N-well region, and apply a third voltage to a port of the P-well region;
wherein when a first operation is performed, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a negative voltage;
when a second operation is performed, the first voltage is a positive voltage, the second voltage is a positive voltage, and the third voltage is a positive voltage.

4 more elements

Dependencies are inferred from the claim text.

Method for operating memory apparatus, memory apparatus, device, and storage medium

Life of this patent

Method for operating memory apparatus, memory apparatus, device, and storage medium

Life of this patent

Abstract

Claims12