Semiconductor memory device

A semiconductor memory device, comprising:

• a memory cell array including a first memory bank and a second memory bank each having a plurality of memory cells, each of the plurality of memory cells being connected to a corresponding word line and a corresponding bit line pair, the number of word lines in the first memory bank being smaller than the number of word lines in the second memory bank;
• and
• a write circuit having a function of lowering a potential of one bit line of a bit line pair connected to a write-target memory cell, and bringing the low potential-side bit line to a negative potential by means of a capacitance connected to an internal ground line in response to a negative potential boost signal,
• wherein
• the capacitance includes a first capacitor element and a second capacitor element each connected to the internal ground line, the low potential-side bit line is brought to a negative potential using only the first capacitor element at the time of write into a memory cell in the first memory bank, and the low potential-side bit line is brought to a negative potential using the first capacitor element and the second capacitor element at the time of write into a memory cell in the second memory bank.