Memory structure including a low cell supply voltage programming circuit

A structure comprising:

• an array of memory cells;
• a first cell supply voltage line connected to the memory cells and at a first cell supply voltage, wherein the first cell supply voltage is programmable;
• and
• a programming circuit connected to the first cell supply volage line and including:
• switches;
• and
• transistors connected to ground and further connectable by the switches, respectively, to the first cell supply voltage line, wherein the transistors are on an insulator layer above a well region in a semiconductor substrate and have different threshold voltages, and wherein the well region is connected to receive a bias voltage.

A structure comprising:

• an array of memory cells;
• a first cell supply voltage line connected to the memory cells and at a first cell supply voltage, wherein the first cell supply voltage is programmable;
• and
• a programming circuit connected to the first cell supply voltage line and including:
• switches;
• and
• transistors connected to ground and further connectable by switches, respectively, to the first cell supply voltage line, wherein the transistors have different threshold voltages and include:
• two N-channel field effect transistors on an insulator layer above a first Nwell in a semiconductor substrate, wherein the first Nwell is connected to receive a first bias voltage;
• and
• two P-channel field effect transistors on the insulator layer above a second Nwell in the semiconductor substrate, wherein the second Nwell is isolated from the first Nwell and connected to receive a second bias voltage.